Device scaling in microelectronics is confined by fundamental physical limits and/or economic constraints. New device concepts and fabrication approaches that may result in integration levels far beyond the limits of conventional microelectronics are constantly being explored. However, the ultimate goal of the exploration is not to simply make the existing electronic components smaller than they are today, but rather to exploit unique properties of the device materials at a nanometer scale to integrate different functions within a single block, to perform conventional functions with less power consumption, or to develop inexpensive fabrication methods driven by self-assembly.
One of the emerging approaches that may overcome the existing limitations is the so-called bottom-up assembly of well-defined nanoscale building blocks (hereinafter, the prefix “nano” refers to a lateral dimension scale of about one tenth of a nanometer to one hundred nanometers). Examples of the nanoscale building blocks include molecule clusters, quantum dots, and nanowires. Properties of these nanoscale building blocks that can be controlled include size, morphology, chemical composition, etc.
In particular, nanowires and carbon nanotubes (CNTs) have been used to construct various functional devices and device arrays, including field effect transistors (FETs), p-n diodes, bipolar junction transistors and integrated logic circuits. These results represent important advances for the nanoelectronics, yet the development of the nanoscale device structures that exhibit new device functions may open up additional and potentially unexpected opportunities for nanoelectronic systems.
As shown in FIG. 1, the elemental building block that lies at the bottom of the fabrication stack in the current semiconductor technology is the metal-oxide-semiconductor field-effect transistor (MOSFET) 10. This device is fabricated via a so-called top-down fabrication method that builds the device structure (including highly doped source region 20 and drain region 30) into an opposite doped semiconductor substrate 50. A source terminal 22 and a drain terminal 32 are deposited on the source region 20 and drain region 30, respectively. A dielectric oxide layer 52 is deposited on the substrate 50 and a gate terminal 42 is deposited on the dielectric layer 52. A back contact layer 54 is deposited on the surface of the substrate opposing the doped source and drain regions.
The MOSFET works by modulating charge concentration using a gate voltage between a body electrode (back contact 54) and the gate terminal 42. With a sufficient gate voltage, electrons from the source enter the area between the source 20 and the drain 30 to form an inversion layer or channel 40 at the interface between the substrate 50 and the dielectric layer 52. This conducting channel 40 extends between the source and the drain, and current is conducted through it when a voltage is applied between the source and the drain.
Currently, the dimensions of the conventional MOSFETs have been scaled down to a few tens of nanometers. Gate lengths as short as 30-40 nm are being routinely produced for modern microprocessors.
Instead of the conventional top-down approach used for many years in microelectronic device fabrication, some semiconductor devices can now be fabricated by a so-called bottom-up process. The bottom-up approach employs a well controlled self-assembly process of atoms to form a nanoscale device structure on a semiconductor substrate. This approach is considered a more precise technique of engineering such devices at the nanometer level. Most of the prior work on the bottom-up FET fabrication concentrates on prototypes based on individual CNTs and nanowires that form a nanostructure. Essentially, the chemically synthesized nanostructure plays the role of a freestanding transistor channel, while source, drain, and gate terminals are later fabricated with top-down nanolithography. A typical example of a transistor structure fabricated by the bottom-up process is shown in FIGS. 2 and 3. A semiconductor nanowire 60 is disposed on a SiO2 substrate 70. Two metal contacts 62 and 64 are deposited on the substrate, connecting via the semiconductor nanowire 60. An insulator layer 66 is deposited on the nanowire 60 and the metal contacts 62 and 64. A third metal contact 68 is deposited on the insulator layer 66 above the nanowire region. The nanowire 60 forms a channel between the two metal contacts 62 and 64 that act as a source terminal and a drain terminal, respectively, and the third metal contact 68 acts as a gate terminal (back contact omitted for simplicity).
However, the above-described example of the bottom-up approach still has a size limitation that is determined by the gate width. As the channel length scales down, it becomes very difficult to precisely align the top gate on the nanowire channel. Therefore, the same challenges and limitations faced by top-down methods still exist in this approach.
In this disclosure, a refined bottom-up fabrication process is revealed. This process is based on easy, inexpensive and large-area fabrication methods for the fabrication of integrated nanodevices.